Integrated Circuits have traditionally implemented a single function, or else functions that were defined by software programming. In either case, however, the logic architecture that implemented the functionality of the circuit was fixed during the design of the integrated circuit. More recently, integrated circuits have been developed whose logic architecture can be changed after manufacture. Field programmable gate arrays (FPGAs), for example, have been developed whose logic functions can be established by the user away from the place where they were manufactured. FPGAs are used in the implementation of random logic networks, data routing, code converters, instruction decoders, state sequencers, and a variety of other functions.
The programming of an FPGA by a user may be accomplished using fuse technology, which involves the physical modification of the manufactured integrated chip so as to connect or disconnect elements in the integrated chip, or by memory programming, which involves setting multiple memory bits on the integrated chip. The memory bits in turn control the connection of elements in the integrated chip. An FPGA typically includes an array of logic blocks and interconnection resources. Each logic block can be programmed to implement a particular function. Signal propagation is accomplished by means of the interconnect resources. By programming multiple logic blocks to implement logic functions and using the interconnect resources to propagate signals, a desired logic circuit can be implemented.
The functionality of an FPGA using static random access memory (SRAM), for example, may be defined by reading in a bitstream and storing it in a configuration memory. A bitstream typically contains a header, data frames and a trailer. The length of the data frames for FPGA chips having different array sizes or different logic capacities, however, is typically different. Problems may occur if a bitstream intended for a certain array size is sent to an FPGA chip with a different array size. The beginning of a data frame, for example, may be detected incorrectly and stop bits may be treated as configuration data. Also, the chip may be erroneously configured in a way that leads to input-output or internal signal contention. As a result, the chip may dissipate a lot of power, thereby harming or destroying the electrical or other characteristics of the chip. Furthermore, if input buffers on the FPGA chip were changed to output buffers, other chips connected to the FPGA may be damaged. Even if the array size of the target FPGA is consistent with the size of the bitstream, different FPGAs may have different routing structures. It is, therefore, desirable to provide a mechanism for verifying the FPGA chip for which a particular bitstream is intended so as to detect and prevent mismatches.